The goal of this blog is to create the verification environment of PCIe..!!! There are three layers in PCIe namely TL(Transaction Layer), DL(Data Link Layer) and PL(Physical Layer). Verification of functional features of these layers is really important. Creating a test bench components around this is really important...!!!
Here are steps used for doing the verification...!!!
1) Understanding the specification for three layers from functionality perspective...!!!
2) Creating the test plan from functional specification..!!!
3) Writing the functional test cases from specification test plan..!!!
4) Running the regressions with specification test cases..!!!
5) Filing the bugs which are found in regressions..!!!
6) Fixing the bugs which are found in regressions..!!!
7) Doing the coverage analysis including functional, code and FSM coverage..!!!
8) Doing the coverage closure with getting the 99.99% pass scenarios..!!!
Strategy for verifying the TL(Transaction Layer):
1) Build testcases around the basic transactions verification like Memory Read, Memory Write, IO Read and IO Write..!!!
2) Build testcases around the error injection scenarios including address out of range and corrupting the normal packets..!!!
3) Build testcases for Virtual Channel and Traffic Class classification..!!!
4) Build testcases for ECRC and Poisoned TLP transactions..!!!
5) Build testcases for Byte Count Transactions..!!!
6) Build testcases for Flow Control Verification..!!!
7) Build test cases for Various Error Scenarios for credit corruptions..!!!
Strategy for verifying DL(Data Link Layer):
1) Build test cases for DLCSM state machine verification..!!!
2) Build test cases for different types of DLLP transactions..!!!
3) Build test cases for sequence number and LCRC corruption..!!!
4) Build test cases for various DLLP packet corruption..!!!
5) Build test cases for various power management transactions..!!!
6) Build test cases for various flow control packet corruptions..!!!
Strategy for verifying PL(Physical Layer):
1) Need to transverse through all the LTSSM states through state transitions..!!!
2) Need to have an error injection scenarios for all the state transitions..!!!
3) Need to have 8b/10b encoding/decoding corruption..!!!
4) Need to have Scrambling and De-Scrambling error..!!!
All the above are an important factors for verifying the PCIe protocol..Verification should be build around this..!!!
I can be reached for questions regarding this at rakeshsachdev2003@gmail.com
Thanks to PCI-SIG for providing specification which made these verification scenarios possible..!!!
Stay Tuned For Next Blog..!!!
Thanks..!!! Have A Great Day..!!!
Here are steps used for doing the verification...!!!
1) Understanding the specification for three layers from functionality perspective...!!!
2) Creating the test plan from functional specification..!!!
3) Writing the functional test cases from specification test plan..!!!
4) Running the regressions with specification test cases..!!!
5) Filing the bugs which are found in regressions..!!!
6) Fixing the bugs which are found in regressions..!!!
7) Doing the coverage analysis including functional, code and FSM coverage..!!!
8) Doing the coverage closure with getting the 99.99% pass scenarios..!!!
Strategy for verifying the TL(Transaction Layer):
1) Build testcases around the basic transactions verification like Memory Read, Memory Write, IO Read and IO Write..!!!
2) Build testcases around the error injection scenarios including address out of range and corrupting the normal packets..!!!
3) Build testcases for Virtual Channel and Traffic Class classification..!!!
4) Build testcases for ECRC and Poisoned TLP transactions..!!!
5) Build testcases for Byte Count Transactions..!!!
6) Build testcases for Flow Control Verification..!!!
7) Build test cases for Various Error Scenarios for credit corruptions..!!!
Strategy for verifying DL(Data Link Layer):
1) Build test cases for DLCSM state machine verification..!!!
2) Build test cases for different types of DLLP transactions..!!!
3) Build test cases for sequence number and LCRC corruption..!!!
4) Build test cases for various DLLP packet corruption..!!!
5) Build test cases for various power management transactions..!!!
6) Build test cases for various flow control packet corruptions..!!!
Strategy for verifying PL(Physical Layer):
1) Need to transverse through all the LTSSM states through state transitions..!!!
2) Need to have an error injection scenarios for all the state transitions..!!!
3) Need to have 8b/10b encoding/decoding corruption..!!!
4) Need to have Scrambling and De-Scrambling error..!!!
All the above are an important factors for verifying the PCIe protocol..Verification should be build around this..!!!
I can be reached for questions regarding this at rakeshsachdev2003@gmail.com
Thanks to PCI-SIG for providing specification which made these verification scenarios possible..!!!
Stay Tuned For Next Blog..!!!
Thanks..!!! Have A Great Day..!!!
